Work in progress
HISIM Chiplet / Systolic-Array Simulator
A hardware design-space exploration tool for chiplet-based systolic-array accelerators — network, memory, and chiplet DSE with a live web workbench on top of the simulation engine.
Checking status…
Note
This is a live development build.
The simulator runs on a personal workstation and is exposed here for preview purposes while it's under active development. It may occasionally be offline or restart, and the link above can change between sessions.